During typical semiconductor manufacturing processes, a plurality of integrated circuits are formed as individual dice on a semiconductor wafer. Each semiconductor wafer generally has dozens to hundreds of individual dice formed thereon. Once the dice are formed on a semiconductor wafer, the dice are then tested to determine which dice are functional and which dice are not functional. In most testing procedures, each die is probed using very costly probe equipment while the dice are still on the wafer. This step is also known as “wafer sort.”
The purpose of the wafer-level probe test is to determine, as early as possible in the manufacturing process, whether each individual die is defective or not. The earlier a defective die is detected, the less time and expense that is wasted on further processing of defective dice. That is, if it is determined that a detected defect cannot be repaired, the time and expense of completing a chip assembly will not be expended.
Traditionally, probe equipment has been capable of only testing one or a few dice at a time. In traditional testing procedures, probe equipment is used to contact each bonding pad (or “access pad”) on an individual die with a separate probe needle. More specifically, in traditional testing procedures, each die is probed in order to determine whether it passes a very basic test (e.g., a test for electrical opens or electrical shorts). In most cases, a full functional test may also be performed using the probe equipment. A probe (which may be referred to herein as a “stylus”) may be brought into contact with one or more bonding pads of a die in order to communicate signals (e.g., a test pattern) to the die and to receive the signals output by the die responsive to the input signals. The probe may be communicatively coupled to an external Automated Test Equipment (ATE) that is operable to generate the signals to be input to a die and to evaluate the signals output by the die in order to determine whether the die is functioning properly. Traditional testing procedures generally involve contacting access pad(s) of each individual die with a probe in series. That is, the dice of a wafer are generally tested one at a time in series using a probe to contact the pad(s) of each die. In some instances a probe card may be utilized that includes a sufficient number of pins to enable multiple dice to be tested concurrently. That is, a probe card may comprise a sufficient number of pins to enable access pads of multiple dice to be contacted simultaneously for testing of such multiple dice. As described further below, it is generally desirable to test a large number of dice in parallel because of the time required for moving the probe card from one die (or set of dice) to another die (or set of dice), which may be on the order of the actual testing time.
Traditional testing procedures are problematic because of their serial nature. For example, using a probe to test one die after another die results in an undesirably long time being required for testing all of the dice of a wafer, which effectively increases the overall cost of testing the dice. Probes used for testing the dice are generally very expensive, and it is therefore undesirable to have a probe tied up for a long time testing each die. Additionally, while certain probe implementations may provide a sufficient number of pins to enable a plurality of dice to be tested simultaneously, such testing is limited by the configuration (e.g., the number of pins) of the probe. For instance, a probe that comprises sufficient pins for contacting two dice simultaneously is limited to testing of two dice concurrently. Thus, if it is desired to test four dice, the probe configuration is incapable of testing all four dice simultaneously. Thus, generally the communication to the dice for testing is limited by the probe card's configuration. In addition, physical constraints may limit the amount of parallelism that may be achieved through modifying a probe's configuration (e.g., to include more pins). For example, in some instances it may not be technologically possible to arrange the pins of a probe in a manner (e.g., sufficiently close together) to enable testing of a desired number of dice, or implementing such an arrangement may not be cost effective.
Further, the life of a probe is generally measured by the number of times it touches down on dice (e.g., a probe may have a typical life of one million touch downs). Traditional testing procedures that require a probe to touch down on one (or a few) dice at a time effectively increases the wear of a probe. For instance, a probe having a life of one million touch downs that is utilized in a traditional testing procedure in which one die at a time is tested will be capable of testing one million dice. Considering the cost associated with such probes, it is generally desirable to effectively prolong the life of a probe by testing as many dice as possible during the probe's life.
More recently, testing techniques have been proposed that enable parallel testing of multiple dice of a wafer with a single probe. Examples of such parallel testing schemes that have been proposed include those described in U.S. Pat. No. 5,504,369 titled “Apparatus for Performing Wafer Level Testing of Integrated Circuit Dice” issued Apr. 2, 1996 to Dasse et al., U.S. Pat. No. 5,898,186 titled “Reduced Terminal Testing System” issued Apr. 27, 1999 to Farnworth et al., and U.S. Pat. No. 6,340,823 B1 titled “Semiconductor Wafer Having a Multi-Test Circuit, and Method for Manufacturing a Semiconductor Device Including Multi-Test Process” issued Jan. 22, 2002 to Kitade. Such parallel testing schemes proposed in the prior art generally provide for one or more wafer-level access pads arranged on a wafer external to the dice, and such access pads may be contacted by a probe to input signals and/or to receive output signals. In these testing schemes, the wafer-level access pads may each be coupled to a plurality of dice, thereby enabling input signals from a probe to be communicated to such plurality of dice in parallel and/or enabling output signals from the plurality of dice to be communicated to the probe.
Parallel testing schemes of the prior art have primarily focused on avoiding contact by a probe with access pads of an individual die in order to prevent damaging the die's access pads. While parallel testing solutions of the prior art propose communicatively coupling a wafer-level access pad to multiple dice to enable data to be communicated from the access pad to the dice in parallel (and vice-versa), such solutions do not provide a communication scheme for improving/optimizing efficiency and reliability of the testing. That is, the primary focus of prior parallel testing solutions has been to arrange wafer-level access pads that are each coupled to a plurality of dice so as to prevent damaging the access pads of the dice with a test probe, and such solutions have neglected to provide an interconnection scheme that enables test data to be communicated from one die to another die in a manner to improve efficiency and/or reliability of the testing. Further, parallel testing solutions proposed in the prior art are difficult and/or not cost effective to manufacture.
Once the wafer-level testing is completed, the dice are usually then separated or singulated into individual die using any one of a variety of singulation techniques. Typically, the dice are singulated by use of a wafer saw, which grinds the wafer along cut zones (usually referred to as “scribe lines”) separating the individual die. In most cases, each die is then packaged in an integrated circuit package. Once the dice have been packaged, thorough electrical testing is typically performed on each of the packaged integrated circuits. The purpose of the thorough electrical testing is to determine whether each packaged integrated circuit properly performs the functionality specified by the designer. The packaged integrated circuits determined to function properly are then sold.
Sometimes process monitors are placed on the scribe lines and on other places of the wafer. Such process monitors typically comprise small circuitry (e.g., a ring oscillator) that is used to measure process parameters. However, this measurement cannot be used to point to certain defects on dies in isolation. It can only be used to get data about different process parameters that impact a portion of the wafer, beyond a single die.
In some cases, the packaged integrated circuits also undergo a reliability testing procedure called burn-in. Burn-in testing involves the testing of an integrated circuit for an extended period of time while its temperature is elevated above room temperature. In some cases, the heat generated by the integrated circuit itself is sufficient to elevate its temperature by a sufficient amount for the burn-in testing. In other cases, the temperature of the integrated circuit is raised by an external apparatus external (e.g. a burn-in oven in which the packaged integrated circuits are placed).
Instead of or in addition to burn-in testing, cold temperature reliability testing may be performed. Cold temperature reliability testing involves the testing of an integrated circuit for an extended period of time while its temperature is decreased below room temperature.
Semiconductor manufacturers spend a significant amount of money packaging defective dice which pass the testing performed during probing, but which do not pass the reliability testing after packaging. The cost saving goal of detecting and screening out defective dice as early as possible in the manufacturing process is especially important in the context of multi-chip modules (MCMs). Multi-chip modules (MCMs) are electronic modules that include a plurality of integrated circuit dice which are packaged together as one unit. Multi-chip modules are becoming more widely used.
For multi-chip modules, it is quite costly to replace one or more failed dice once the dice have been bonded onto a substrate. Therefore, it is desirable to determine whether a die is fully functional and is reliable before the die is packaged as part of a multi-chip module. In addition, many manufacturers of multi-chip modules are requiring that semiconductor manufacturers sell them fully tested “known good dice” that have passed reliability tests and that are not packaged in an integrated circuit package.